The Single Wire Protocol (SWP) is a specification for a single-wire connection Master Analog Front End (AFE) between the SIM card or smart card (SWP slave) and a near field communication (NFC) chip (SWP master) in a cell phone. It was under final review by the European Telecommunications Standards Institute (ETSI). The technical specification (TS) for SWP was produced by ETSI Technical Committee Smart Card Platform (SCP) under the ETSI TS 102 613 specification.

SWP is an interface between contactless frontend (CLF) and universal integrated circuit card (UICC/SIM card chip). It is a contact-based protocol that is used for contactless communication. C6 pin of UICC is connected to CLF for SWP support. It is a bit-oriented full duplex protocol i.e. at the same time transmission as well as reception is possible. CLF acts as a master and UICC as a slave. CLF provides the UICC with energy, a transmission clock, data, and a signal for bus management. The data to be transmitted are represented by the binary states of voltage and current on the single wire.

ETSI TS 102 613 document is to ensure interoperability between a UICC and the CLF in the terminal independently of the respective manufacturer, card issuer or operator. Any internal technical realization of either the UICC or the CLF is only specified where these are reflected over the interface.

The ETSI TS 102 613 document defines:

  • Layer1: The physical layer which is responsible for activating, maintaining and deactivating the physical link between the UICC and the CLF. It defines electrical (voltage and current levels, timing and coding of voltage and current levels), mechanical (physical contacts) and functional (data rates) specifications. It also defines the initial communication establishment and the end of the connection.
  • Layer 2: The data link layer which is responsible for the physical addressing of the data through frames and Link Protocol Data Units (LPDU). The data link layer is also responsible for error notification, ordered delivery of frames and flow control. This layer can be split into two sub-layers:
    • The Medium Access Control (MAC) layer which manages frames.
    • The Logical Link Control layer which manages LPDUs and is responsible for the error-free exchange of data between nodes. Three different Logical Link Control layers are defined in the present document.
  • Operating junction temperature range: -40°C to +125°C
    Silicon proven in a 130 nm and 55 nm CMOS processes
    Characteristics of a 130 nm implementation:
    • typical operating current consumption smaller than 100 µA
    • typical standby current consumption smaller than 1 µA
    • silicon area (including a 80 µm x 80 µm pad) smaller than 0.03 mm²
  • Straightforward integration through a standard interface (customized on request)

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