NXP JCOP 4 Java Card 3.0.5 Classic

NXP JCOP 4 Java Card 3.0.5 Classic


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The JCOP 4 is NXP Semiconductors N.V. latest 3rd generation SmartMX platform built for the digital services era to provide advanced security and privacy protection for citizen IDs, ePassports, payment and access management applications. The JCOP 4 operating system runs on the latest Java Card 3.0.5 Classic with GlobalPlatform 2.3.

Uncompromising on performance and security, the platform is optimized to create future-proof secure microprocessors required for secure identity and payment applications where protection of personal identifiable information (PII) and other private data are paramount.

SmartMX3 products build on the proven and reliable IntegralSecurity 2.0 architecture, which demonstrates worldwide interoperability and standard compliance. The new generation of NXP’s proven and reliable SmartMX microcontroller family delivers the highest security and best-in-class performance across all target applications. The powerful P71D321 security controller is the first solution released in the new SmartMX3 family and is Common Criteria EAL6+ certified.

The SmartMX3 P71D321 secure element platform does not only provide a first-choice hardware solution but also offers built-in high-performance libraries for communication, memory control, and cryptography modules to enhance performance and significantly shorten development cycles. Moreover, NXP® is offering a full system solution powered by JCOP operating system. Running JCOP 4 on the P71D321 guarantees a perfect match of hardware and software capabilities resulting in excellent performance figures and enabling the fastest time to market approach for upcoming security solutions.


EMV: J2R100, J2R150, J2R200, J3R100, J3R150, J3R200

SECID: J2R110, J2R150, J2R180, J3R110, J3R150, J3R180



  • Best-in-class performance:
    • < 200ms for a M/Chip transaction
    • < 2s for ePassport SAC
  • Broadest reader interoperability by self-tuned EMD noise reduction
  • Fast operating system download to flash memory (100KB/s) MRK3-SC 16/32-bit RISC (reduced instruction set computing) CPU for high transaction performance, low power consumption and world-class security level
  • Code Signature ensures the integrity of instruction execution



  • First payment and secure identification device implemented in CMOS40 technology
  • Full flash memory solution up to 344 KB
  • Up to 200 KB non-volatile memory available
  • Most advanced RF front end technology to maximize communication sensitivity



  • Advanced IntegralSecurity 3.0 architecture
  • EMVCo and CC EAL 6+ (PP 0084 with loader package 2) certification taking latest attacks on security into accountual-interface applications
  • Fully certified symmetric, hash and asymmetric cryptography libraries
    • Top-level cryptography engines with “full key length” support
    • Dedicated cryptography functional unit for symmetric DES and AES algorithms
    • 56-bit key length DES, 112-bit 2DES, 168-bit triple-DES (TDES or 3DES), in various configurations
    • AES with 128, 192 and 256-bit key length
    • Asymmetric cryptography accelerator unit, supporting RSA, ECC and related algorithms
    • RSA cryptography with arbitrary key length up to 4096 bits
    • Elliptic-curve cryptography (ECC) with key length up to 571 bits
  • True Random Number Generator, compliant to AIS31
  • Deterministic Random Number Generator for faster execution in cases where lower
  • RNG entropy is sufficient
  • SPA and DPA prevention
  • PKCC protection
  • PUF: interface to the physical unclonable function provided by the hardware


  • Multi-application enabled by MIFARE FleX® with MIFARE® DESFire® EV2 up to 16KB and MIFARE Plus® EV1 up to 4KB (including MIFARE Classic® support)
  • Optional implementation of software libraries to accelerate time to market
  • Full system solution available with JCOP® 4 operating system
  • Broad portfolio of payment and secure identification applets Customer Support Package
  • Well established SmartCard Composer development environment
  • Soft-mask device to accelerate hardware validation
  • Full set of system documentation and customer trainings



  • Best-in-class performance and excellent RF communication
  • Optimized total cost of ownership
  • One-stop shop system solution available (including hardware, libraries and solutions)
Add-on Feature EMV/SECID
OS features
ISO/IEC14443(2016) Y
Java Card 3.0.5 Classic Y
GlobalPlatform ID Configuration v1.0 Y
GlobalPlatform Common Implementation Configuration v2.0 Y
GlobalPlatform Card Financial Configuration Y
GlobalPlatform Mapping Guidelines Y
EMV4.3 Y
EMV CL 2.6 Y
Suppport for PUF (physical unclonable function) Y
CL EAL6+,EMV Open Platform,BCTC OS Y
Cryptographic features
Data Encryption Standard (DES) and dual/triple key DES via coprocessor Y
  • AES via coprocessor:
  • Up to 4096 bit
  • Up to 2048 bit
Other cryptographic support such as SHA-1,SHA-224,SHA-256,SHA-384,SHA-512 and CRC 16&32 according to ISO 3309 Y
RSA key gen add-on RSA key generation -/Selectable
ECC add-on
  • ECC via coprocessor (up to 521 bit)
  • ECC key gen
Korean Seed add-on -Secure Korean Seed algorithm(KTFC certified) Selectable/-
Contact interface with T=0 and T=1 protocols

According to ISO/IEC 7816

Contactless interface with T=CL protocol

According to ISO/IEC 14443 Type A(2016)

Java Card and GlobalPlatform features
Java Card 3.0.5 Classic Y
Inter-applet PIN sharing Y
Loader Service ready Y
Secure in-field applet download Y
DRG.3 compliant pseudo-random number generator Y
SECID add-on
  • Support for ISO compliance and ICAO9303-1
  • Machine Readable Travel Documents Part 1
  • SAC and PACE support
  • Secure Messaging Accelerator (eGovAccelerator)
  • Additional JCOP APIs
Biometric features
MoC ID3 add-on Biometric APIs Selectable
MoC Neurotechnology add-on Biometric APIs Selectable
Other features
FIPS add-on -/Selectable
Secure Box Secure native execution of 3rd party libraries Y
Config Module Used for OS initialization Y


EMVCo payment card (MasterCard, Visa, American Express, Discover and other payment applications)

Cryptocurrency secure storage

Electronic Health Record (EHR or EMR)

ISO-18013 International Driving License BAP and EAP

European Citizen Card (EN 15480)

ICAO Electronic passport (ePassport) providing BAC, EACv1 and SAC/PACE support

European Health Insurance Card (EHIC) (CDA 15974-2009E)

Fingerprint Match on Card(ISO19794)-MINEX III compliant

SECID applications such as ePKI, eVR and eRP


Java Card version 3.0.5 Classic
Global Platform version 2.3
Security evaluation and certificates
  • Common criteria CC EAL6+
  • EMVCo (VISA, CAST), FIPS certified
  • RSA up to 4096-bit key generation
  • ECC (Elliptic-curve cryptography) with key length up to 571 bits
  • AES encryption and decryption up to 256-bit
  • SHA1/SHA224/SHA256/SHA512 hash algorithm
  • DES/3DES encryption and decryption 56/112/168-bit
  • ECDSA up to 521-bit
  • True Random Number Generator (TRNG)
  • DPA Timing Analysis and Fault Induction protection
  • Diffie-Hellman with ECDH and modular exponentiation
  • PUF (Physical Unclonable Function)
EEPROM: up to 200 KB user memory
  • 100K: J2R100, J3R100 (EMV)
  • 110K: J2R110, J3R110 (SECID)
  • 150K: J2R150, J3R150 (EMV & SECID)
  • 180K: J2R180, J3R180 (SECID)
  • 200K: J2R200, J3R200 (EMV)

Data retention time: 25 years minimum

Endurance: 500000 cycles minimum

ROM: up to 192 KB
RAM: 12 KB for none MIFARE configurations (Less RAM is available when MIFARE Plus EV1 or MIFARE DESFire EV2 emulation is active)
CMOST Technology: CMOS040/ter
Support of major Public Key Cryptography (PKC) systems such as RSA, Elgamel,
DSS, Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves
Enhanced high-performance secured Public Key Infrastructure (PKI) coprocessor
(RSA, ECC) Fame2
Enhanced high-performance secured hardware support for symmetric block cipher (SBC) algorithms
  • Secured dual/triple-DES coprocessor
  • Secured AES coprocessor
  • Multiple key and data register sets supporting parallel data/key loading and calculation
ISO/IEC 7816 contact interface 
  • ISO/IEC 7816 contact interface (UART) offering hardware support for ISO/IEC 7816 T=0 and T=1 protocol stack implementation
  • support of concurrent operation of both ISO/IEC 7816 and ISO/IEC 14443 interface
  • continuous operation from 1.62 V up to 5.5 V supported
ISO/IEC 14443 contactless interface 
  • ISO/IEC 14443A Contactless Interface Unit (CIU) supporting data rates of 106 kbit/s, 212 kbit/s, 424 kbit/s, 848 kbit/s and offering hardware support for ISO/IEC 14443 T=CL protocol stack implementation
  • Very High Baud Rate (VHBR) is supported for PICC to PCD up to 3.2MBit/sec
Communication Protocol Contact interface supports T=1 (default) and T=0*
Default ATR:
Secure Channel Protocol:
  • SCP01 (i=05)
  • SCP02 (i=05, i=15, i=35, i=45, i=55, i=75)
  • SCP03 (i=00, i=10, i=20, i=60, i=70)
Part Numbers Model:

EMV: J2R100, J2R150, J2R200, J3R100, J3R150, J3R200

SECID: J2R110, J2R150, J2R180, J3R110, J3R150, J3R180

Secure Smart Card Controller SmartMX3 P71 P71D321

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